Memory provides data storage for electronic systems. Flash memory is one type of memory, and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.
NAND may be a basic architecture of flash memory, and may be configured to comprise vertically-stacked memory cells. Example NAND architecture is described in U.S. Pat. Nos. 7,898,850 and 8,778,762, and in U.S. Patent Publication Nos. 2014/0191306 and 2014/0131784.
FIG. 1 shows a block diagram of a prior art device 100 which includes a memory array 102 having a plurality of memory cells 103 arranged in rows and columns along with access lines 104 (e.g., wordlines to conduct signals WL0 through WLm) and first data lines 106 (e.g., bitlines to conduct signals BL0 through BLn). Access lines 104 and first data lines 106 may be used to transfer information to and from the memory cells 103. Row decoder circuitry 107 and column decoder circuitry 108 decode address signals A0 through AX on address lines 109 to determine which ones of the memory cells 103 are to be accessed. Driver circuitry 91 may be utilized in conjunction with the row decoder circuitry to drive a selected wordline 104, and similarly driver circuitry 93 may be utilized in conjunction with the column decoder circuitry to drive a selected data line 106. A sense amplifier circuit 115 operates to determine the values of information read from the memory cells 103. An I/O circuit 117 transfers values of information between the memory array 102 and input/output (I/O) lines 105. Signals DQ0 through DQN on the I/O lines 105 can represent values of information read from or to be written into the memory cells 103. Other devices can communicate with the device 100 through the I/O lines 105, the address lines 109, or the control lines 120. A memory control unit 118 controls memory operations to be performed on the memory cells 103 utilizing signals on the control lines 120. The device 100 can receive supply voltage signals Vcc and Vss on a first supply line 130 and a second supply line 132, respectively. The first and second supply lines 130 and 132 may be coupled with a power management circuit 95. Also, other components of device 100 may be coupled with the power management circuit, although such electrical couplings are not specifically shown in FIG. 1.
The device 100 includes a select circuit 140 which may be utilized with the input/output (I/O) circuit 117. The select circuit 140 can respond, via the I/O circuit 117, to signals CSEL1 through CSELn to select signals on the first data lines 106 and the second data lines 113 that can represent the values of information to be read from or to be programmed into the memory cells 103. The column decoder circuitry 108 can selectively activate the CSEL1 through CSELn signals based on the A0 through AX address signals on the address lines 109. The select circuit 140 can select the signals on the first data lines 106 and the second data lines 113 to provide communication between the memory array 102 and the I/O circuit 117 during read and programming operations.
FIG. 2 shows a block diagram of a prior art memory array (e.g., the memory array 102 of FIG. 1) in the form of a 3D NAND memory device 200. The device 200 may comprise a plurality of strings of charge storage devices. In a first (e.g., Z-Z′) direction, each string of charge storage devices may comprise, for example, thirty two charge storage devices stacked over one another with each charge storage device corresponding to one of, for example, thirty two tiers (e.g., Tier0-Tier31). The charge storage devices of a respective string may share a common channel region, such as one formed in a respective pillar of semiconductor material (e.g., polysilicon) about which the string of charge storage devices are formed. In a second (e.g., X-X′) direction, each first group of, for example, sixteen first groups of the plurality of strings may comprise, for example, eight strings sharing a plurality (e.g., thirty two) of access lines (WLs). Each of the plurality of access lines (hereinafter used interchangeably with “global control gate (CG) lines”) may couple (e.g., electrically or otherwise operably connect) the charge storage devices corresponding to a respective tier of the plurality of tiers of each string of a corresponding one of the first groups. The charge storage devices coupled by the same access line (and thus corresponding to the same tier) may be logically grouped into, for example, two pages, such as P0/P32, P1/P33, P2/P34 and so on, when each charge storage device comprises a multi-level cell capable of storing two bits of information. In a third (e.g., Y-Y′) direction, each second group of, for example, eight second groups of the plurality of strings may comprise sixteen strings coupled by a corresponding one of eight data lines (BLs). The CGs of the (e.g., sixteen) charge storage devices corresponding to a respective tier of the (e.g., sixteen) strings of each second group of strings may be physically coupled by a respective plate. Similarly, SGSs of the (e.g., sixteen) strings of each second group of strings may be physically coupled by a single plate. The size of a memory block may comprise 1,024 pages and total about 16 MB (e.g., 16 WLs×32 Tiers×2 bits=1,024 pages/block, block size=1,024 pages×16 KB/page=16 MB). The number of the strings, tiers, access lines, data lines, first groups, second groups and/or pages may be greater or smaller than those shown in FIG. 2.
FIG. 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of FIG. 2 in an X-X′ direction, including fifteen strings of charge storage devices in one of the sixteen first groups of strings described with respect to FIG. 2. The plurality of strings of the memory block 300 may be grouped into a plurality of subsets 310, 320, 330 (e.g., tile columns), such as tile columnl, tile columnj and tile columnK, with each subset (e.g., tile column) comprising a “partial block” of the memory block 300. A global drain-side select gate (SGD) line 340 may be coupled to the SGDs of the plurality of strings. For example, the global SGD line 340 may be coupled to a plurality (e.g., three) of sub-SGD lines 342, 344, 346 with each sub-SGD line corresponding to a respective subset (e.g., tile column), via a corresponding one of a plurality (e.g., three) of sub-SGD drivers 332, 334, 336. Each of the sub-SGD drivers 332-336 may concurrently couple or cut off the SGDs of the strings of a corresponding partial block (e.g., tile column) independently of those of other partial blocks. A global source-side select gate (SGS) line 360 may be coupled to the SGSs of the plurality of strings. For example, the global SGS line 360 may be coupled to a plurality of sub-SGS lines 362, 364, 366 with each sub-SGS line corresponding to the respective subset (e.g., tile column), via a corresponding one of a plurality of sub-SGS drivers 322, 324, 326. Each of the sub-SGS drivers 322, 324, 326 may concurrently couple or cut off the SGSs of the strings of a corresponding partial block (e.g., tile column) independently of those of other partial blocks. A global access line (e.g., a global CG line) 350 may couple the charge storage devices corresponding to the respective tier of each of the plurality of strings. Each global CG line (e.g., the global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of a plurality of sub-string drivers 312, 314 and 316. Each of the sub-string drivers may concurrently couple or cut off the charge storage devices corresponding to the respective partial block and/or tier independently of those of other partial blocks and/or other tiers. The charge storage devices corresponding to the respective subset (e.g., partial block) and the respective tier may comprise a “partial tier” (e.g., a single “tile”) of charge storage devices. The strings corresponding to the respective subset (e.g., partial block) may be coupled to a corresponding one of sub-sources 372, 374 and 376 (e.g., “tile source”) with each sub-source being coupled to a respective power source.
FIG. 4 shows a region of a prior art semiconductor wafer. Such region is subdivided amongst a plurality of individual die 400. The die may all be substantially identical to one another, and ultimately the die may be singulated into individual units suitable for incorporation into individual packages. For instance, each die may correspond to a memory chip.
FIG. 5 shows an example singulated die 400 from the region identified as region 5 of FIG. 4. The illustrated die 400 comprises a memory array region 102 (also identified as the Array (A)), row decoder circuitry 107 (also identified as Row (R)), column decoder circuitry 108 (also identified as Col (C)), a peripheral region 412 (also identified as Peri (P)), and a bonding pad region 414 (also identified as Bonding Pad (B)). Additionally, a memory control unit (MCU) 118 is shown to be within the peripheral region 412.
The die of FIG. 5 may be considered to be an example of a two-dimensional arrangement, in that no components are stacked under the array 102. In contrast, FIG. 6 shows a prior art die 400a illustrating an example three-dimensional arrangement. The array 102 is divided amongst a plurality of tiles (T) 420, and each tile has column decoder circuitry (C) 108 and row decoder circuitry (R) 107 under the array 102, (the regions 107 and 108 are shown in phantom view relative to one of the tiles to indicate that they are under the array region). Also, drivers (D) 91/93 are within each tile and under the array region.
The configuration of FIG. 6 advantageously saves die area by stacking the row and column decoder circuitries under the array. The tiles may be utilized in an effort to reduce wordline resistance and/or bitline resistance across an array while maintaining desired access speeds. However, the tile configuration introduces additional complications and associated expenses into die fabrication and array programming. It is desired to develop new arrangements of various components of memory chips which save die area, and which enable desired access speeds to be achieved.